Invention Grant
- Patent Title: Dual-stripline with crosstalk cancellation
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Application No.: US17214111Application Date: 2021-03-26
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Publication No.: US12113265B2Publication Date: 2024-10-08
- Inventor: Albert Sutono , Xiaoning Ye
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/49
- IPC: H01L23/49 ; H01L23/498 ; H01L23/528 ; H01L23/66 ; H01P3/08 ; H05K1/02

Abstract:
Electronic structures including a dual-stripline with crosstalk cancellation are described. In an example, a printed circuit board (PCB), a package substrate or a semiconductor die includes a dual-stripline structure. The dual-stripline structure includes a first region including a first top line vertically over a first bottom line, and a second top line vertically over a second bottom line. The dual-stripline structure also includes a second region including the first top line vertically over the second bottom line, and the second top line vertically over the first bottom line. The dual-stripline structure also includes a transition region between the first region and the second region. The first bottom line and the second bottom line cross in the transition region.
Public/Granted literature
- US20220311114A1 DUAL-STRIPLINE WITH CROSSTALK CANCELLATION Public/Granted day:2022-09-29
Information query
IPC分类: