Invention Grant
- Patent Title: Chip package structure with cavity in interposer
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Application No.: US18359923Application Date: 2023-07-27
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Publication No.: US12125755B2Publication Date: 2024-10-22
- Inventor: Shin-Puu Jeng , Feng-Cheng Hsu , Shuo-Mao Chen
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
- Current Assignee Address: TW Hsinchu
- Agency: McClure, Qualey & Rodack, LLP
- The original application number of the division: US16984382 2020.08.04
- Main IPC: H01L23/13
- IPC: H01L23/13 ; H01L23/00 ; H01L23/498 ; H01L23/538 ; H01L25/00 ; H01L25/18

Abstract:
A package structure and a method of forming the same are provided. The package structure includes a package substrate, an interposer substrate, and a semiconductor device. The interposer substrate is disposed over the package substrate, wherein the interposer substrate has a bottom surface facing the package substrate and a first cavity formed on the bottom surface. The semiconductor device is disposed in the first cavity. The package substrate has a top surface facing the interposer substrate and a second cavity formed on the top surface, wherein the second cavity is configured to accommodate the semiconductor device.
Public/Granted literature
- US20230369150A1 CHIP PACKAGE STRUCTURE WITH CAVITY IN INTERPOSER Public/Granted day:2023-11-16
Information query
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