Invention Grant
- Patent Title: Semiconductor package and method
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Application No.: US17242704Application Date: 2021-04-28
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Publication No.: US12125798B2Publication Date: 2024-10-22
- Inventor: Chen-Hua Yu , Jeng-Shien Hsieh , Chuei-Tang Wang , Chieh-Yen Chen
- Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
- Applicant Address: TW Hsinchu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Current Assignee Address: TW Hsinchu
- Agency: Slater Matsil, LLP
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L21/56 ; H01L21/683 ; H01L23/00 ; H01L23/31 ; H01L25/065

Abstract:
A semiconductor device includes a first plurality of dies on a wafer, a first redistribution structure over the first plurality of dies, and a second plurality of dies on the first redistribution structure opposite the first plurality of dies. The first redistribution structure includes a first plurality of conductive features. Each die of the first plurality of dies are bonded to respective conductive features of the first plurality of conductive features by metal-metal bonds on a bottom side of the first redistribution structure. Each die of the second plurality of dies are bonded to respective conductive features of the first plurality of conductive features in the first redistribution structure by metal-metal bonds on a top side of the first redistribution structure.
Public/Granted literature
- US20220352082A1 Semiconductor Package and Method Public/Granted day:2022-11-03
Information query
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