Invention Grant
- Patent Title: MOS transistor having substantially parallelepiped-shaped insulating spacers
-
Application No.: US17180197Application Date: 2021-02-19
-
Publication No.: US12125899B2Publication Date: 2024-10-22
- Inventor: Arnaud Regnier , Dann Morillon , Franck Julien , Marjorie Hesse
- Applicant: STMICROELECTRONICS (ROUSSET) SAS
- Applicant Address: FR Rousset
- Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee: STMICROELECTRONICS (ROUSSET) SAS
- Current Assignee Address: FR Rousset
- Agency: Seed IP Law Group LLP
- Priority: FR 50048 2018.01.04
- The original application number of the division: US16228032 2018.12.20
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/28 ; H01L21/8234 ; H01L21/84 ; H01L27/12 ; H01L29/417 ; H01L29/423 ; H01L29/78 ; H01L29/786
Abstract:
A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
Public/Granted literature
- US20210175346A1 MOS TRANSISTOR SPACERS AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2021-06-10
Information query
IPC分类:
