Invention Grant
- Patent Title: Dynamic configuration of a computer processor based on the presence of a hypervisor
-
Application No.: US18054858Application Date: 2022-11-11
-
Publication No.: US12131178B2Publication Date: 2024-10-29
- Inventor: Steven Jeffrey Wallach
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Greenberg Traurig
- Main IPC: G06F9/455
- IPC: G06F9/455 ; G06F9/4401 ; G06F12/1009 ; G06F9/48 ; G06F13/10

Abstract:
Systems, apparatuses, and methods related to a hypervisor status register in a computer processor are described. For example, a memory coupled to the computer processor can store instructions of routines of predefined, non-hierarchical domains. The computer processor can store a value in the hypervisor status register during a power up process of the computer system. The value stored in the hypervisor status register that identifies whether or not an operating hypervisor is present in the computer system. The computer processor can configure its operations (e.g., address translation) based on the value stored in the hypervisor status register.
Public/Granted literature
- US20230074273A1 DYNAMIC CONFIGURATION OF A COMPUTER PROCESSOR BASED ON THE PRESENCE OF A HYPERVISOR Public/Granted day:2023-03-09
Information query