Invention Grant
- Patent Title: Method for fabricating semiconductor package
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Application No.: US18354668Application Date: 2023-07-19
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Publication No.: US12132021B2Publication Date: 2024-10-29
- Inventor: Chia-Kuei Hsu , Ming-Chih Yew , Po-Hao Tsai , Po-Yao Lin , Shin-Puu Jeng
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- The original application number of the division: US16129736 2018.09.12
- Main IPC: H01L23/31
- IPC: H01L23/31 ; H01L21/56 ; H01L21/768 ; H01L23/00

Abstract:
A redistribution structure includes a first dielectric layer, a pad pattern, and a second dielectric layer. The pad pattern is disposed on the first dielectric layer and includes a pad portion and a peripheral portion. The pad portion is embedded in the first dielectric layer, wherein a lower surface of the pad portion is substantially coplanar with a lower surface of the first dielectric layer. The peripheral portion surrounds the pad portion. The second dielectric layer is disposed on the pad pattern and includes a plurality of extending portions extending through the peripheral portion.
Public/Granted literature
- US20230361070A1 METHOD FOR FABRICATING SEMICONDUCTOR PACKAGE Public/Granted day:2023-11-09
Information query
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