- Patent Title: Bonding and isolation techniques for stacked transistor structures
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Application No.: US18392379Application Date: 2023-12-21
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Publication No.: US12132079B2Publication Date: 2024-10-29
- Inventor: Kuan-Kan Hu , Han-De Chen , Ku-Feng Yang , Chen-Fong Tsai , Chi On Chui , Szuya Liao
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsin-Chu
- Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- Current Assignee Address: TW Hsinchu
- Agency: HAYNES AND BOONE, LLP
- Main IPC: H01L29/06
- IPC: H01L29/06 ; H01L21/8238 ; H01L25/07 ; H01L27/092 ; H01L29/423 ; H01L29/66 ; H01L29/775 ; H01L29/786

Abstract:
Bonding and isolation techniques for stacked device structures are disclosed herein. An exemplary method includes forming a first insulation layer on a first device component, forming a second insulation layer on a second device component, and bonding the first insulation layer and the second insulation layer. The bonding provides a stacked structure that includes the first device component over the second device component, and an isolation structure (formed by the first insulation layer bonded to the second insulation layer) therebetween. The isolation structure includes a first portion having a first composition and a second portion having a second composition different than the first composition. The method further includes processing the stacked structure to form a first device disposed over a second device, where the isolation structure separates the first device and the second device. The first insulation layer and the second insulation layer may include the same or different materials.
Public/Granted literature
- US20240282814A1 Bonding and Isolation Techniques for Stacked Transistor Structures Public/Granted day:2024-08-22
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