Invention Grant
- Patent Title: Memory array
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Application No.: US18170557Application Date: 2023-02-17
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Publication No.: US12133390B2Publication Date: 2024-10-29
- Inventor: Chao-I Wu , Yu-Ming Lin , Sai-Hooi Yeong
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: JCIPRNET
- Main IPC: H10B51/20
- IPC: H10B51/20 ; H01L21/28 ; H01L29/51 ; H10B41/23 ; H10B51/00 ; H10B51/10 ; H10B51/30

Abstract:
Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.
Public/Granted literature
- US20230209835A1 MEMORY ARRAY Public/Granted day:2023-06-29
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