Invention Grant
- Patent Title: ECC configuration in memories
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Application No.: US17802053Application Date: 2021-09-23
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Publication No.: US12135610B2Publication Date: 2024-11-05
- Inventor: Graziano Mirichigni , Christophe Laurent , Riccardo Muzzetto
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Brooks, Cameron & Huebsch, PLLC
- International Application: PCT/IB2021/022216 WO 20210923
- International Announcement: WO2023/047149 WO 20230330
- Main IPC: G06F11/10
- IPC: G06F11/10 ; G06F11/07

Abstract:
The present disclosure relates to a method for operating an array of memory cells, the method comprising storing user data in a plurality of memory cells of the array, storing parity data associated with the user data in a plurality of parity cells of the array, and, based on the stored parity data, selecting an Error Correction Code (ECC) correction capability and/or an ECC granularity according to which an ECC operation is to be performed, wherein the selection of the ECC correction capability and/or the ECC granularity is determined by the steps of updating a first register, said first register comprising values which indicate a required ECC correction capability and/or a required ECC granularity to be applied to the memory cells based on a current status of said memory cells, wherein the values of the first register are updated based on a variation of the current status of the memory cells, and wherein an update of the values of the first register corresponds to a variation of the required ECC correction capability and/or a required ECC granularity to be applied to said memory cells, and based on the updated values of the first register, executing an ECC switch command, wherein the ECC switch command is such as to vary a previously selected ECC correction capability and/or a previously selected ECC granularity, the method further comprising: updating a second register according to the varied ECC correction capability and/or ECC granularity, said second register comprising values indicating the selected ECC correction capability and the selected ECC granularity applied to the memory cells based on the current status thereof. Related apparatuses and systems are also herein disclosed.
Public/Granted literature
- US20240211347A1 IMPROVED ECC CONFIGURATION IN MEMORIES Public/Granted day:2024-06-27
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