Disclosed are an SPI controller and a method of operating an SPI controller. The SPI controller includes: an SPI clock signal generator; a register group configured to store SPI operating configuration of the SPI controller; SPI pins configured to connect to one or more SPI peripherals;
and an input/output controller configured to perform data input or output between the SPI controller and the SPI peripherals according to the SPI clock signal and the SPI operating configuration; an SPI state machine configured to control a working state of the SPI controller. The SPI controller is electrically coupled via a bus to a CPU, a DMA controller, and a system memory located outside the SPI controller; and the input/output controller is further configured to receive an updated SPI operating configuration from the DMA controller and to update the updated SPI operating configuration into the register group between two consecutive SPI transmissions.