A control circuit of a display panel, and a display device. The control circuit of a display panel is configured to receive a first clock signal, a first level signal and a second level signal, phase-shift the first clock signal to obtain a second clock signal according to the first level signal and the second level signal and output the second clock signal to a gate drive circuit. The clock signal is phase-shifted to reduce the load of a single clock signal and minimize the number of clock generators in the display panel, thereby reducing the production cost of the display panel.