Invention Grant
- Patent Title: 3DIC structure for high voltage device on a SOI substrate
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Application No.: US17572891Application Date: 2022-01-11
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Publication No.: US12136627B2Publication Date: 2024-11-05
- Inventor: Harry-Hak-Lay Chuang , Wen-Tuo Huang , Hsin Fu Lin , Wei Cheng Wu
- Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Eschweiler & Potashnik, LLC
- Main IPC: H01L21/762
- IPC: H01L21/762 ; H01L21/768 ; H01L23/48 ; H01L27/12

Abstract:
In some embodiments, the present disclosure relates to a device that includes a silicon-on-insulator (SOI) substrate. A first semiconductor device is disposed on a frontside of the SOI substrate. An interconnect structure is arranged over the frontside of the SOI substrate and coupled to the first semiconductor device. A shallow trench isolation (STI) structure is arranged within the frontside of the SOI substrate and surrounds the first semiconductor device. First and second deep trench isolation (DTI) structures extend from the STI structure to an insulator layer of the SOI substrate. Portions of the first and second DTI structures are spaced apart from one another by an active layer of the SOI substrate. A backside through substrate via (BTSV) extends completely through the SOI substrate from a backside to the frontside of the SOI substrate. The BTSV is arranged directly between the first and second DTI structures.
Public/Granted literature
- US20220415930A1 3DIC STRUCTURE FOR HIGH VOLTAGE DEVICE ON A SOI SUBSTRATE Public/Granted day:2022-12-29
Information query
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