Invention Grant
- Patent Title: Semiconductor structure with a first lower electrode layer and a second lower electrode layer and method for manufacturing same
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Application No.: US17669544Application Date: 2022-02-11
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Publication No.: US12137550B2Publication Date: 2024-11-05
- Inventor: Deyuan Xiao , Lixia Zhang
- Applicant: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Applicant Address: CN Hefei
- Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
- Current Assignee Address: CN Hefei
- Agency: Syncoda LLC
- Agent Feng Ma
- Priority: CN202110807121.7 20210716
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L29/786

Abstract:
A semiconductor structure and a method for manufacturing same. The semiconductor structure includes a storage unit, which includes: a first dielectric layer and a metal bit line located therein; a semiconductor channel, located on the metal bit line; a word line, disposed surrounding part of the semiconductor channel; a second dielectric layer, located between the metal bit line and the word line, and on top of the word line; a first and a second lower electrode layers, stacked on the semiconductor channel, the first lower electrode layer contacting the top surface of the semiconductor channel; an upper electrode layer, located on top of the second lower electrode layer, and surrounding the first and the second lower electrode layers; and a capacitor dielectric layer, located between the upper electrode layer and the first lower electrode layer, and between the upper electrode layer and the second lower electrode layer.
Public/Granted literature
- US20230019891A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING SAME Public/Granted day:2023-01-19
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