Invention Grant
- Patent Title: Memory array and method used in forming a memory array
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Application No.: US17395211Application Date: 2021-08-05
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Publication No.: US12137553B2Publication Date: 2024-11-05
- Inventor: Sidhartha Gupta , Naveen Kaushik , Pankaj Sharma
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wells St. John P.S.
- Main IPC: H10B41/27
- IPC: H10B41/27 ; H01L23/538 ; H10B43/27

Abstract:
A method used in forming a memory array comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. Channel-material strings of memory-cell strings extend through the insulative and conductive tiers. Conductive vias are formed above and individually electrically coupled to individual of the channel-material strings. Insulating material is laterally-between immediately-adjacent of the conductive vias. At least some of the insulating material is vertically removed to form an upwardly-open void-space that is circumferentially about multiple of the conductive vias. Insulative material is formed laterally-between the immediately-adjacent conductive vias to form a covered void-space from the upwardly-open void-space. Digitlines are formed above that are individually electrically coupled to a plurality of individual of the conductive vias there-below. Other embodiments, including structure independent of method, are disclosed.
Public/Granted literature
- US20230039621A1 Memory Array And Method Used In Forming A Memory Array Public/Granted day:2023-02-09
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