A semiconductor memory device may include a second conductive type first well, a second conductive type third well, a first conductive type second well, a floating gate and a selection gate. The first well may include a first active region. The third well may include a third active region. The second well may be arranged between the first well and the third well. The second well may include a second active region. The floating gate may be overlapped with the first active region, the second active region and the third active region. The selection gate may be overlapped with the second active region. The selection gate and the floating gate may be arranged side by side. A second overlap area between the second active region and the floating gate may be larger than a third overlap area between the third active region and the floating gate.