Integration of ferroelectric memory devices having stacked electrodes with transistors

Invention Grant

US12137574B2 Integration of ferroelectric memory devices having stacked electrodes with transistors 有权

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Patent Title: Integration of ferroelectric memory devices having stacked electrodes with transistors
Application No.: US18357974

Application Date: 2023-08-15
Publication No.: US12137574B2

Publication Date: 2024-11-05
Inventor: Sasikanth Manipatruni , Rajeev Kumar Dokania , Ramamoorthy Ramesh , Gaurav Thareja , Amrita Mathuriya
Applicant: Kepler Computing Inc.
Applicant Address: US CA San Francisco
Assignee: Kepler Computing Inc.
Current Assignee: Kepler Computing Inc.
Current Assignee Address: US CA San Francisco
Agency: MUGHAL GAUDRY & FRANKLIN PC
Main IPC: H10B53/30
IPC: H10B53/30 ; G11C11/22 ; H01L49/02

Integration of ferroelectric memory devices having stacked electrodes with transistors

Abstract:

Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Public/Granted literature

US20240099018A1 INTEGRATION OF FERROELECTRIC MEMORY DEVICES HAVING STACKED ELECTRODES WITH TRANSISTORS Public/Granted day:2024-03-21

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