Invention Grant
- Patent Title: Wafer inspection system
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Application No.: US17723723Application Date: 2022-04-19
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Publication No.: US12148144B2Publication Date: 2024-11-19
- Inventor: Chia-Lin Tsai , Hung-Ru Li , Wun-Ye Ku
- Applicant: NANYA TECHNOLOGY CORPORATION
- Applicant Address: TW New Taipei
- Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee: NANYA TECHNOLOGY CORPORATION
- Current Assignee Address: TW New Taipei
- Agent Xuan Zhang
- Main IPC: G06T7/00
- IPC: G06T7/00 ; G06V10/22 ; G06V10/74

Abstract:
A wafer inspection system is provided. The wafer inspection system includes a memory unit configured to store an image of a device under test (DUT) on a wafer, an image-uploading unit configured to upload the image to a processing unit, and a processing unit. The processing unit is configured to identify a plurality of candidate regions on the image; generate a confidence score for each of the plurality of candidate regions, wherein the confidence score indicates a probability of a candidate region including a probe mark; select a first candidate region having the highest confidence score as a selected region; determine whether a second candidate region in the plurality of candidate regions includes the same probe mark as the first candidate region; and eliminate the second candidate region if the second candidate region includes the same probe mark as the first candidate region.
Public/Granted literature
- US20230334647A1 WAFER INSPECTION SYSTEM Public/Granted day:2023-10-19
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