A method (of forming a three dimensional integrated circuit (3DIC) structure) includes: forming an interconnection layer including forming a first inter-layer via which connects at a first predetermined location to a first circuit region of a first device layer and which has a footprint that is at least one factor of ten smaller than a footprint of the first circuit region; and forming a first conductive segment in a first metallization layer of a second device layer so as to align with and thereby connect to the first inter-layer via.