Invention Grant
- Patent Title: Connection arrangements for integrated lateral diffusion field effect transistors having a backside contact
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Application No.: US17660721Application Date: 2022-04-26
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Publication No.: US12159815B2Publication Date: 2024-12-03
- Inventor: Shanghui Larry Tu , Michael A. Stuber , Befruz Tasbas , Stuart B. Molin , Raymond Jiang
- Applicant: Silanna Asia Pte Ltd
- Applicant Address: SG Singapore
- Assignee: Silanna Asia Pte Ltd
- Current Assignee: Silanna Asia Pte Ltd
- Current Assignee Address: SG Singapore
- Agency: MLO, a professional corp.
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/535 ; H01L23/66 ; H01L27/12 ; H01L29/06 ; H01L29/417 ; H01L29/66 ; H01L29/78 ; H01L29/786 ; H01L21/8234 ; H01L27/088 ; H01L29/08 ; H01L29/40

Abstract:
A semiconductor package includes a leadframe having an electrically conductive paddle, electrically conductive perimeter package leads, a first electrically conductive clip electrically connected to a first set of the package leads, and a second electrically conductive clip electrically connected to a second set of the package leads. The semiconductor package includes a single semiconductor die. The die includes a front-side active layer having an integrated power structure of two or more transistors. The die includes a backside portion having a backside contact electrically coupled to at least one of the two or more transistors and to the paddle. One or more first front-side contacts of the die are electrically coupled to at least one of the transistors and to the first clip, and one or more second front-side contacts of the die are electrically coupled to at least one of the transistors and to the second clip.
Public/Granted literature
Information query
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