Invention Grant
- Patent Title: Scalable and interoperable PHYLESS die-to-die IO solution
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Application No.: US16910023Application Date: 2020-06-23
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Publication No.: US12159840B2Publication Date: 2024-12-03
- Inventor: Zhiguo Qian , Gerald Pasdast , Juan Zeng , Peipei Wang , Ahmad Siddiqui , Lakshmipriya Seshan
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/495
- IPC: H01L23/495 ; H01L23/00 ; H01L23/538

Abstract:
Embodiments disclosed herein include multi-die packages with interconnects between the dies. In an embodiment, an electronic package comprises a package substrate, and a first die over the package substrate. In an embodiment, the first die comprises a first IO bump map, where bumps of the first IO bump map have a first pitch. In an embodiment, the electronic package further comprises a second die over the package substrate. In an embodiment, the second die comprises a second IO bump map, where bumps of the second IO bump map have a second pitch that is different than the first pitch. In an embodiment, the electronic package further comprises interconnects between the first IO bump map and the second IO bump map.
Public/Granted literature
- US20210398906A1 SCALABLE AND INTEROPERABLE PHYLESS DIE-TO-DIE IO SOLUTION Public/Granted day:2021-12-23
Information query
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