Semiconductor structures and methods for forming same are disclosed. In one form, a structure includes: a base, including a first device region and a second device region, where the first device region includes a channel region, and preset regions located on two sides of the channel region, and a well pick-up region surrounding the channel region and the preset regions; a first isolation structure, located in the base between the preset regions and the well pick-up region and between the well pick-up region and the adjacent second device region; a poly gate, covering the channel region; a first source/drain doping region, located in the preset regions on two sides of the poly gate; a metal gate, located on the base in the second device region; a support structure, located on the top of the first isolation structure; and an interlayer dielectric layer, covering side walls of the poly gate, the metal gate, and the support structure. The support structure can mitigate a problem of top surface dishing of the interlayer dielectric layer above the first isolation structure, to avoid contacting the first source/drain doping region and the well pick-up region in a planarization process of forming the interlayer dielectric layer and the metal gate, thereby improving the performance of the semiconductor structure.