A clock doubler circuit doubles the frequency of an input clock signal. The input clock signal is supplied to a duty cycle corrector (DCC) circuit, which generates a DCC output signal having a duty cycle corrected to fifty percent and has a frequency that equals the input frequency. A T/4 delay circuit receives the input clock signal and generates a T/4 delay output signal that has a delay of T/4 from the DCC output signal and has the same frequency as the input clock signal. T/4 is one quarter of a period of the input clock signal. An XOR gate combines the DCC output signal and the T/4 delay output signal to generate an output clock signal that is twice the frequency of the input clock signal. A duty cycle estimator generates correction factors used to generate the T/4 delay output signal and the DCC output signal.