- Patent Title: Multiple incremental redundancy scheme using linear rateless codes
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Application No.: US17863283Application Date: 2022-07-12
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Publication No.: US12166575B2Publication Date: 2024-12-10
- Inventor: David Yunusov , Gideon Shlomo Kutz
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Holland & Hart LLP
- Main IPC: H04L1/00
- IPC: H04L1/00 ; H03M13/00 ; H03M13/11

Abstract:
Methods, systems, and devices for wireless communications are described. In some examples, a first device may combine, for each of a set of sub-blocks of a block of data, a set of unencoded bits associated with a respective sub-block with a matrix to generate a set of encoded bits. The first device may transmit a first message including the block to a second device. The second device may determine respective probabilities of successful decoding of respective selected candidate codewords for the set of sub-blocks of the block based on receiving the first message and may transmit one or more indicators associated with one or more sub-blocks based on the respective probabilities of successful decoding of the respective selected candidate codewords. The first device may transmit a second message including redundancy information for the one or more sub-blocks based on transmitting the one or more indicators.
Public/Granted literature
- US20240022350A1 MULTIPLE INCREMENTAL REDUNDANCY SCHEME USING LINEAR RATELESS CODES Public/Granted day:2024-01-18
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