Techniques are disclosed relating to object and mesh shaders executed by a graphics processor. In some embodiments, a device includes buffer circuitry and shader circuitry configured to execute graphics programs. Control circuitry may: generate object shader work and mesh shader work for the shader circuitry, receive output information generated by a mesh shader that indicates a number of vertices and primitives to be output by the mesh shader, allocate, based on the output information and after execution of at least a portion of the mesh shader, a region of the buffer circuitry for storage of the vertices to be output by the mesh shader, and store the vertices output by the mesh shader in the allocated region. Disclosed techniques may advantageously provide efficient use of limited buffer resources.