Invention Grant
- Patent Title: Iterative decoder for correcting dram device failures
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Application No.: US17896994Application Date: 2022-08-26
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Publication No.: US12170531B2Publication Date: 2024-12-17
- Inventor: Joseph M. McCrate , Nevil Gajera , Mohammed Ebrahim Hargan
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Wood IP LLC
- Agent Theodore A. Wood
- Main IPC: H03M13/15
- IPC: H03M13/15 ; H03M13/37

Abstract:
Provided is a memory system comprising an error correction code (ECC) decoder configured to receive data from a memory. The ECC decoder includes a syndrome generator configured to calculate at least one of syndrome vector and an erasure value, the calculation being devoid of erasure location information and an error-location polynomial generator configured to determine error location and error/erasure value polynomials responsive to syndrome and erasure calculation values output from the syndrome generator. An error value generator confirms error values at one or more known error locations based upon the determined error/erasure value polynomials, and an error location generator search for an error evaluation value to confirm the known error locations based upon the determined error location polynomials. Outputs of the error value generator and the error location generator are combined to produce corrected data.
Public/Granted literature
- US20230223961A1 ITERATIVE DECODER FOR CORRECTING DRAM DEVICE FAILURES Public/Granted day:2023-07-13
Information query
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