Semiconductor memory device and method of manufacturing the semiconductor memory device
Abstract:
According to one embodiment, a semiconductor memory device includes interconnect layers stacked above a substrate; a memory pillar configured to penetrate the interconnect layers; a first member and a second member; and a dividing portion provided between the first member and the second member. The dividing portion includes insulating layers. The insulating layers each include a first portion and a second portion. The first portion is provided between the first member and the second portion. The second portion is provided between the first portion and the second member. The first portion and the second portion each have an individual arc shape when viewed from a top and are in contact with each other.
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