- Patent Title: Single port memory with multiple memory operations per clock cycle
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Application No.: US18090574Application Date: 2022-12-29
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Publication No.: US12190994B2Publication Date: 2025-01-07
- Inventor: Kumar Rahul , Santosh Yachareni , Mahendrakumar Gunasekaran , Mohammad Anees
- Applicant: XILINX, INC.
- Applicant Address: US CA San Jose
- Assignee: XILINX, INC.
- Current Assignee: XILINX, INC.
- Current Assignee Address: US CA San Jose
- Agency: Patterson + Sheridan, LLP
- Main IPC: G11C7/22
- IPC: G11C7/22 ; G11C7/10

Abstract:
An integrated circuitry (IC) device for a memory device includes driver circuitry, selection circuitry, clock generation circuitry, and self-time path circuitry. The driver circuitry generates a plurality of driver circuitry outputs. The selection circuitry selects one of the plurality of driver circuitry outputs based on a plurality of enable signals. The clock generation circuitry receives the selected one of the plurality of driver circuitry outputs from the selection circuitry, and generates a clock signal based on at least the selected one of the plurality of driver circuitry outputs from the selection circuitry. The self-time path circuitry of a memory receives the clock signal and generates a reset signal based on the clock signal. The plurality of driver circuitry outputs and the clock signal are based on the reset signal, and the self-time path circuitry corresponds to one or more columns of a memory bank.
Public/Granted literature
- US20240221808A1 SINGLE PORT MEMORY WITH MUTLITPLE MEMORY OPERATIONS PER CLOCK CYCLE Public/Granted day:2024-07-04
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