Invention Grant
- Patent Title: Packaging structure and method for preparing same
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Application No.: US17478806Application Date: 2021-09-17
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Publication No.: US12198942B2Publication Date: 2025-01-14
- Inventor: Jangshen Lin , Chengchung Lin , Yenheng Chen
- Applicant: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Applicant Address: CN Jiangyin
- Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee: SJ SEMICONDUCTOR (JIANGYIN) CORPORATION
- Current Assignee Address: CN Jiangyin
- Agency: IPRTOP LLC
- Priority: CN202010989133.1 20200918,CN202022055491.3 20200918
- Main IPC: H01L21/48
- IPC: H01L21/48 ; H01L23/00 ; H01L23/15 ; H01L23/34 ; H01L23/48 ; H01L23/498 ; H01L25/065

Abstract:
The present disclosure provides a chip packaging structure and a method for preparing the same. The packaging structure includes a glass substrate, metal connecting posts, a first packaging layer, a connection layer, semiconductor chips, a filler layer, a second packaging layer, a controlled collapse chip connection (C4) layer, a base substrate, and a heat sink housing. In the present disclosure, metal connecting posts are pre-formed in a glass substrate, so that the glass substrate serves as an intermediate conduction layer, and the semiconductor chips and the C4 layer are respectively formed at opposite ends of the metal connecting posts to perform electrical connections, so that the number of process steps for preparing the packaging structure is minimized and the manufacturing cost is reduced.
Public/Granted literature
- US20220093415A1 PACKAGING STRUCTURE AND METHOD FOR PREPARING SAME Public/Granted day:2022-03-24
Information query
IPC分类: