- Patent Title: Semiconductor circuit including latch circuit for error correction
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Application No.: US18252360Application Date: 2021-11-10
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Publication No.: US12199613B2Publication Date: 2025-01-14
- Inventor: Lui Sakai , Yasuo Kanda , Masahiro Segami , Keizo Hiraga
- Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Applicant Address: JP Kanagawa
- Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
- Current Assignee Address: JP Kanagawa
- Agency: CHIP LAW GROUP
- Priority: JP2020-191177 20201117
- International Application: PCT/JP2021/041395 WO 20211110
- International Announcement: WO2022/107670 WO 20220527
- Main IPC: H03K3/037
- IPC: H03K3/037 ; G11C11/16 ; G11C29/42 ; H03K3/3562 ; G11C11/417
Abstract:
A semiconductor circuit according to an embodiment of the present disclosure includes a nonvolatile latch circuit that stores k-bit data, and m-bit error correction data for the k-bit data.
Public/Granted literature
- US20240014810A1 SEMICONDUCTOR CIRCUIT Public/Granted day:2024-01-11
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