Invention Grant
- Patent Title: Load reduced memory module
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Application No.: US18604133Application Date: 2024-03-13
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Publication No.: US12200860B2Publication Date: 2025-01-14
- Inventor: Frederick A. Ware , Suresh Rajan
- Applicant: Rambus Inc.
- Applicant Address: US CA San Jose
- Assignee: Rambus Inc.
- Current Assignee: Rambus Inc.
- Current Assignee Address: US CA San Jose
- Agency: Lowenstein Sandler LLP
- Main IPC: G11C5/06
- IPC: G11C5/06 ; G06F1/18 ; G06F13/16 ; G06F13/40 ; G06F15/78 ; G11C5/04 ; G11C7/10 ; G11C11/408 ; G11C11/4093 ; H05K1/11 ; H05K1/18

Abstract:
The embodiments described herein describe technologies for memory systems. One implementation of a memory system includes a motherboard substrate with multiple module sockets, at least one of which is populated with a memory module. A first set of data lines is disposed on the motherboard substrate and coupled to the module sockets. The first set of data lines includes a first subset of point-to-point data lines coupled between a memory controller and a first socket and a second subset of point-to-point data lines coupled between the memory controller and a second socket. A second set of data lines is disposed on the motherboard substrate and coupled between the first socket and the second socket. The first and second sets of data lines can make up a memory channel.
Public/Granted literature
- US20240276639A1 LOAD REDUCED MEMORY MODULE Public/Granted day:2024-08-15
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