Invention Grant
- Patent Title: Method of fabricating semiconductor device having bit line comprising a plurality of pins extending toward the substrate
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Application No.: US18219722Application Date: 2023-07-10
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Publication No.: US12200923B2Publication Date: 2025-01-14
- Inventor: Janbo Zhang , Li-Wei Feng , Yu-Cheng Tung
- Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
- Applicant Address: CN Quanzhou
- Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee: Fujian Jinhua Integrated Circuit Co., Ltd.
- Current Assignee Address: CN Quanzhou
- Agent Winston Hsu
- Priority: CN202110499195.9 20210508,CN202120968517.5 20210508
- Main IPC: H10B12/00
- IPC: H10B12/00 ; H01L27/092 ; H01L29/06 ; H01L29/66

Abstract:
The present disclosure relates to a method of fabricating a semiconductor device, the semiconductor device includes a substrate, a plurality of gate structures, a plurality of isolation fins, and at least one bit line. The gate structures are disposed in the substrate, with each of the gate structures being parallel with each other and extending along a first direction. The isolation fins are disposed on the substrate, with each of the isolation fins being parallel with each other and extending along the first direction, over each of the gate structures respectively. The at least one bit line is disposed on the substrate to extend along a second direction being perpendicular to the first direction. The at least one bit line comprises a plurality of pins extending toward the substrate, and each of the pins is alternately arranged with each of the isolation fins along the second direction.
Public/Granted literature
- US20230354583A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE Public/Granted day:2023-11-02
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