A 3D AND flash memory device includes a gate stack structure, a channel stack structure, a source pillar and a drain pillar, and a plurality of charge storage structures. The gate stack structure is located on the dielectric substrate. The gate stack structure includes a plurality of gate layers and a plurality of insulating layers stacked alternately with each other. The channel stack structure extends through the gate stack structure. The channel stack structure includes a plurality of channel rings spaced apart from each other. The source pillar and the drain pillar are located in the channel stack structure and are respectively electrically connected to the plurality of channel rings. The plurality of charge storage structures are located between the plurality of gate layers and the plurality of channel rings.