A vertical non-volatile memory device capable of stably maintaining an operating temperature in a chip level, a semiconductor package including the memory device, and a heat dissipation method of the memory device. The vertical non-volatile memory device includes a substrate on which a cell array area and an extension area are defined, a vertical channel structure formed on the substrate, a thermoelectric device including at least two semiconductor pillars formed on the substrate, and a stacked structure on the substrate. The stacked structure includes a gate electrode layer and an interlayer insulation layer which are stacked alternately along sidewalls of the vertical channel structure and the at least two semiconductor pillars. The at least two semiconductor pillars include an n-type semiconductor pillar and a p-type semiconductor pillar which are electrically connected to each other through a conductive layer on the substrate.