Invention Grant
- Patent Title: Layout for dual in-line memory to support 128-byte cache line processor
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Application No.: US18048911Application Date: 2022-10-24
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Publication No.: US12211577B2Publication Date: 2025-01-28
- Inventor: Radoslav Danilak , Rodney Mullendore , William Radke , Chi To
- Applicant: TACHYUM LTD.
- Applicant Address: US NV Las Vegas
- Assignee: TACHYUM LTD.
- Current Assignee: TACHYUM LTD.
- Current Assignee Address: US NV Las Vegas
- Agency: GREENBLUM & BERNSTEIN, P.L.C.
- Main IPC: G11C5/04
- IPC: G11C5/04 ; G11C7/10 ; G11C7/22 ; G11C11/4076 ; H05K1/18

Abstract:
A memory stick configured for use with a processor in a computer is provided. The memory stick includes a printed circuit board with first and second sides, each of the first and second sides including eighteen memory chips, each of the memory chips being an ×8 DRAM chip; the eighteen memory chips being distributed into first, second, third and fourth rows, the first row and the second row being on a left half of the printed circuit board and the third and fourth row being on a right half of the printed circuit board; and the printed circuit board including at least 400 pins including at least 16 pins for ECC bits and at least 128 pins for data bits; wherein at least the memory chips and the 128 pins for data bits establish a 128-bit data width to communicate.
Public/Granted literature
- US20230132146A1 LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCESSOR Public/Granted day:2023-04-27
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