Invention Grant
- Patent Title: Group III-V IC with different sheet resistance 2-DEG resistors
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Application No.: US17462743Application Date: 2021-08-31
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Publication No.: US12211835B2Publication Date: 2025-01-28
- Inventor: Dong Seup Lee , Hiroyuki Tomomatsu
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Andrew R. Ralston; Frank D. Cimino
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L27/06 ; H01L29/66 ; H01L49/02
Abstract:
An integrated circuit (IC) includes a lower group III-N layer having a first composition over a substrate, and an upper group III-N layer having a different second composition over the lower group III-N layer. A gate electrode of a High Electron Mobility Transistor (HEMT) is located over the upper group III-N layer. First and second resistor contacts make a conductive connection to the lower group III-N layer. An unbiased group III-N cover layer is located on the upper group III-N layer in a resistor area including a high Rs 2-DEG resistor, where the unbiased group III-N cover layer is positioned between the first and second contacts.
Public/Granted literature
- US20230065509A1 GROUP III-V IC WITH DIFFERENT SHEET RESISTANCE 2-DEG RESISTORS Public/Granted day:2023-03-02
Information query
IPC分类:
