The present disclosure relates to a latch, a processor including the latch, and a computing apparatus. A latch with an inverted output is provided, including: an input stage configured to receive a latch input; an output stage configured to output a latch output; an intermediate node disposed between an output of the input stage and an input of the output stage, wherein the output stage is configured to receive a signal at the intermediate node as an input; and a feedback stage configured to receive the latch output and provide a feedback to the intermediate node, wherein feedback stage assumes a logic-high state, a logic-low state, and a high-impedance state, wherein the latch output is inverted from the latch input.