Various embodiments of the present disclosure are directed towards an integrated chip including a piezoelectric membrane overlying a substrate. A plurality of conductive layers is disposed within the piezoelectric membrane. The plurality of conductive layers comprises a first conductive layer over a second conductive layer. The first conductive layer comprises a first electrode and the second conductive layer comprises a second electrode. A first conductive via is disposed in the piezoelectric membrane and contacts the first electrode. A second conductive via is disposed in the piezoelectric membrane and contacts the second electrode. A sidewall of the second conductive via comprises a vertical sidewall segment overlying a slanted sidewall segment.