Invention Grant
- Patent Title: Nested interposer with through-silicon via bridge die
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Application No.: US17186289Application Date: 2021-02-26
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Publication No.: US12218040B2Publication Date: 2025-02-04
- Inventor: Srinivas V. Pietambaram , Debendra Mallik , Kristof Darmawikarta , Ravindranath V. Mahajan , Rahul N. Manepalli
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L23/00 ; H01L23/498 ; H01L25/065

Abstract:
An electronic package includes an interposer having an interposer substrate, a cavity that passes into but not through the interposer substrate, a through interposer via (TIV) within the interposer substrate, and an interposer pad electrically coupled to the TIV. The electronic package includes a nested component in the cavity, wherein the nested component includes a component pad coupled to a through-component via. A core via is beneath the nested component, the core via extending from the nested component through the interposer substrate. A die is coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect.
Public/Granted literature
- US20220278032A1 NESTED INTERPOSER WITH THROUGH-SILICON VIA BRIDGE DIE Public/Granted day:2022-09-01
Information query
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