Invention Grant
- Patent Title: Semiconductor device including a dielectric layer between a source/drain region and a substrate
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Application No.: US18366733Application Date: 2023-08-08
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Publication No.: US12219748B2Publication Date: 2025-02-04
- Inventor: Kam-Tou Sio , Yi-Hsun Chiu
- Applicant: Taiwan Semiconductor Manufacturing Company Limited
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
- Current Assignee Address: TW Hsinchu
- Agency: Jones Day
- Main IPC: H10B10/00
- IPC: H10B10/00 ; H01L29/423 ; H01L29/66 ; H01L29/78 ; H01L29/786

Abstract:
Devices and methods are described herein that obviate the need for a read assist circuit. In one example, a semiconductor device includes a source region and a drain region formed above a substrate. A buried insulator (BI) layer is formed beneath either the source region or the drain region. A first nano-sheet is formed (i) horizontally between the source region and the drain region and (ii) vertically above the BI layer. The BI layer reduces current flow through the first nano-sheet.
Public/Granted literature
- US20230389259A1 Semiconductor Device Including a Layer Between a Source/Drain Region and a Substrate Public/Granted day:2023-11-30
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