Generating source code adapted for implementation on FPGAs
Abstract:
A method for generating source code includes: transforming a block diagram into an intermediate representation, wherein transforming the block diagram into the intermediate representation comprises transforming at least two blocks, wherein at least one loop results from transforming an operation block; identifying at least one candidate loop in the intermediate representation, wherein a loop body of a candidate loop comprises at least one instruction that accesses the array variable; identifying at least one parallelizable loop from the at least one candidate loop; determining build options for the at least one parallelizable loop and the array variable; inserting build pragmas based on the determined build options in the intermediate representation; and translating the intermediate representation into the source code.
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