Invention Grant
- Patent Title: Semiconductor package having side wall plating
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Application No.: US17436454Application Date: 2019-03-08
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Publication No.: US12224232B2Publication Date: 2025-02-11
- Inventor: Barry Lin
- Applicant: SILICONIX INCORPORATED
- Applicant Address: US CA San Jose
- Assignee: SILICONIX INCORPORATED
- Current Assignee: SILICONIX INCORPORATED
- Current Assignee Address: US CA San Jose
- Agency: Volpe Koenig
- International Application: PCT/US2019/021272 WO 20190308
- International Announcement: WO2020/185192 WO 20200917
- Main IPC: H01L21/56
- IPC: H01L21/56 ; H01L23/00 ; H01L23/31 ; H01L23/495

Abstract:
Techniques are disclosed herein for forming a dual flat no-leads semiconductor package. The techniques begin with a package assembly that includes multiple non-singulated packages. The semiconductor package assembly includes a lead frame assembly having dies coupled thereto. A mold encapsulation covers at least portions of the dies and exposes a plurality of leads. A first cutting step exposes sidewalls of leads of the lead frame. An electroplating step deposits a plating on the exposed leads. A second cutting step cuts through the mold encapsulation aligned with the step cut sidewalls. A third cutting step perpendicular to the step cuts and is made through the lead frame and mold encapsulation to singulate the dies into individual packages.
Public/Granted literature
- US20220181239A1 SEMICONDUCTOR PACKAGE HAVING SIDE WALL PLATING Public/Granted day:2022-06-09
Information query
IPC分类: