A circuitry (30) for on-chip power regulation is provided. The circuitry (30) comprises a memory array (31) comprising a plurality of memory cell blocks (32) arranged in rows and columns, where the memory cell blocks are clustered into a defined number of memory cell blocks (33) along the row, each cluster (33) is connected to a respective local reference line (34). In addition, the circuitry (30) comprises a plurality of sense amplifiers (40) connected to the respective memory cell blocks (32). The circuitry (30) further comprises at least one dummy memory cell block (35) additionally arranged to each cluster of memory cell blocks (33), where the dummy memory cell block (35) is connected to a main reference line (36). Moreover, the circuitry (30) comprises at least one transistor (37) arranged in between the local reference line (34) of each cluster of memory cell blocks (33) and the main reference line (36).