Invention Grant
- Patent Title: Stacked transistors with different channel widths
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Application No.: US17979345Application Date: 2022-11-02
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Publication No.: US12230544B2Publication Date: 2025-02-18
- Inventor: Kangguo Cheng , Lawrence A. Clevenger , Balasubramanian S. Pranatharthiharan , John Zhang
- Applicant: Adeia Semiconductor Solutions LLC
- Applicant Address: US CA San Jose
- Assignee: Adeia Semiconductor Solutions LLC
- Current Assignee: Adeia Semiconductor Solutions LLC
- Current Assignee Address: US CA San Jose
- Agency: Haley Guiliano LLP
- Main IPC: H01L23/535
- IPC: H01L23/535 ; G06F30/39 ; G06F30/392 ; H01L21/02 ; H01L21/306 ; H01L21/768 ; H01L21/8234 ; H01L27/02 ; H01L27/088 ; H01L29/06 ; H01L29/08 ; H01L29/40 ; H01L29/423 ; H01L29/45 ; H01L29/49 ; H01L29/66 ; H01L29/775 ; H01L29/78 ; H01L29/786

Abstract:
A semiconductor device includes a first stack of nanowires above a substrate with a first gate structure over, around, and between the first stack of nanowires and a second stack of nanowires above the substrate with a second gate structure over, around, and between the second stack of nanowires. The device also includes a first source/drain region contacting a first number of nanowires of the first nanowire stack and a second source/drain region contacting a second number of nanowires of the second nanowire stack such that the first number and second number of contacted nanowires are different.
Public/Granted literature
- US20230298941A1 STACKED TRANSISTORS WITH DIFFERENT CHANNEL WIDTHS Public/Granted day:2023-09-21
Information query
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