Invention Grant
- Patent Title: Semiconductor devices having highly integrated sheet and wire patterns therein
-
Application No.: US17571954Application Date: 2022-01-10
-
Publication No.: US12230630B2Publication Date: 2025-02-18
- Inventor: Kyung In Choi , Do Young Choi , Dong Myoung Kim , Jin Bum Kim , Hae Jun Yu
- Applicant: Samsung Electronics Co., Ltd.
- Applicant Address: KR Suwon-si
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: MORGAN, LEWIS & BOCKIUS LLP
- Priority: KR10-2021-0075786 20210611
- Main IPC: H01L27/088
- IPC: H01L27/088 ; H01L21/8234

Abstract:
A semiconductor device includes a semiconductor substrate having first and second regions therein, a first lower semiconductor pattern, which protrudes from the semiconductor substrate in the first region and extends in a first direction across the semiconductor substrate, and a first gate electrode, which extends across the first lower semiconductor pattern and the semiconductor substrate in a second direction. A plurality of semiconductor sheet patterns are provided, which are spaced apart from each other in a third direction to thereby define a vertical stack of semiconductor sheet patterns, on the first lower semiconductor pattern. A first gate insulating film is provided, which separates the plurality of semiconductor sheet patterns from the first gate electrode. A second lower semiconductor pattern is provided, which protrudes from the semiconductor substrate in the second region. A plurality of wire patterns are provided, which are spaced apart from each other on the second lower semiconductor pattern. A second gate insulating film is wrapped around each of the plurality of wire patterns.
Public/Granted literature
- US20220399330A1 SEMICONDUCTOR DEVICES HAVING HIGHLY INTEGRATED SHEET AND WIRE PATTERNS THEREIN Public/Granted day:2022-12-15
Information query
IPC分类: