Invention Grant
- Patent Title: Method for making nanostructure transistors with source/drain trench contact liners
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Application No.: US18613557Application Date: 2024-03-22
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Publication No.: US12230694B2Publication Date: 2025-02-18
- Inventor: Donghun Kang
- Applicant: Atomera Incorporated
- Applicant Address: US CA Los Gatos
- Assignee: Atomera Incorporated
- Current Assignee: Atomera Incorporated
- Current Assignee Address: US CA Los Gatos
- Agency: ALLEN, DYER, DOPPELT, + GILCHRIST, P.A. Attorneys at Law
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/06 ; H01L29/08 ; H01L29/15 ; H01L29/16 ; H01L29/161 ; H01L29/417 ; H01L29/423 ; H01L29/775 ; H01L29/786

Abstract:
A method for making a semiconductor device may include forming spaced apart gate stacks on a substrate with adjacent gate stacks defining a respective trench therebetween. Each gate stack may include alternating layers of first and second semiconductor materials, with the layers of the second semiconductor material defining nanostructures. The method may further include forming respective source/drain regions within the trenches, respective insulating regions adjacent lateral ends of the layers of the first semiconductor material, and respective conductive contact liners in the trenches.
Public/Granted literature
- US20240322015A1 METHOD FOR MAKING NANOSTRUCTURE TRANSISTORS WITH SOURCE/DRAIN TRENCH CONTACT LINERS Public/Granted day:2024-09-26
Information query
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