Invention Grant
- Patent Title: Type III-V semiconductor device with structured passivation
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Application No.: US17667927Application Date: 2022-02-09
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Publication No.: US12230700B2Publication Date: 2025-02-18
- Inventor: Simone Lavanga , Nicholas Dellas , Gerhard Prechtl , Luca Sayadi
- Applicant: Infineon Technologies Austria AG
- Applicant Address: AT Villach
- Assignee: Infineon Technologies Austria AG
- Current Assignee: Infineon Technologies Austria AG
- Current Assignee Address: AT Villach
- Agency: Murphy, Bilak & Homiller, PLLC
- Main IPC: H01L29/778
- IPC: H01L29/778 ; H01L21/02 ; H01L21/76 ; H01L21/765 ; H01L23/29 ; H01L23/31 ; H01L29/20 ; H01L29/205 ; H01L29/40 ; H01L29/66

Abstract:
A high-electron-mobility transistor comprises a semiconductor body comprising a barrier region and a channel region that forms a heterojunction with the barrier region such that a two-dimensional charge carrier gas channel is disposed in the channel region, source and drain electrodes disposed on the semiconductor body and laterally spaced apart from one another, a gate structure disposed on the semiconductor body and laterally between the source and drain electrodes, the gate structure being configured to control a conduction state of two-dimensional charge carrier gas, and a first dielectric region that is disposed along the upper surface of the semiconductor body in a lateral region that is between the gate structure and the drain electrode, wherein the first dielectric region comprises aluminum and oxide, and wherein first dielectric region comprises a first end that faces and is laterally spaced apart from the gate structure.
Public/Granted literature
- US20230253486A1 TYPE III-V SEMICONDUCTOR DEVICE WITH STRUCTURED PASSIVATION Public/Granted day:2023-08-10
Information query
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