An ADC includes a comparator to provide a comparator output responsive to an input voltage of the ADC and a DAC output voltage; a SAR circuit including a SAR that stores an n-bit digital code that is initialized at a beginning of a conversion phase of the ADC, where the SAR circuit is to update the digital code responsive to the comparator output, where an ADC output is responsive to the digital code at an end of the conversion phase; and a DAC to provide the DAC output voltage responsive to the digital code and a reference voltage. The DAC includes an m-bit CDAC and an (n−m)-bit RDAC to provide an intermediate voltage responsive to the n−m least-significant bits of the digital code and the reference voltage. The CDAC provides the DAC output voltage responsive to the m most-significant bits of the digital code, the intermediate voltage, and reference voltage.