A device includes a decoder configured to identify, during an intra-block copy (IBC) decoding process on at least a portion of a coding unit of video data, a target virtual address in a virtual address space associated with a read operation of the IBC decoding process. The target virtual address is generated according to an addressing scheme of an on-chip memory used by the IBC decoding process. The decoder is configured to identify, based on the target virtual address, an on-chip memory start address of a portion of the on-chip memory. The on-chip memory is configured to store reconstructed blocks of the video data. The decoder is also configured to perform the read operation to read a block of pixel data from the on-chip memory using the on-chip memory start address.