In a vertical power device with trenched insulated gates, there is an npnp layered structure. The vertical gates turn on the device with a suitable gate bias to conduct a current between a top electrode and a bottom electrode. In an example, implanted n+ source regions are formed in the top surface within a p-well. Between some gates, the overlying dielectric is opened up, by etching, to expose distributed p-type contact regions for the p-well. The dielectric is also opened up to expose areas of the n+ source regions. The top electrode metal directly contacts the exposed p-type contact regions and the n+ source regions to provide distributed emitter-to-base short across the cellular array to improve device performance in the presence of transients. The p-contact regions are isolated from the n+ source regions, prior to the deposition of the metal electrode, due to the p-type contact regions not abutting the n+ source regions.