An arithmetic device includes an activation function (AF) control circuit, a data storage circuit, and an output distribution signal generation circuit. The AF control circuit generates a column address, a data selection signal, and an internal control signal based on an arithmetic result signal during an activation operation. The data storage circuit outputs activation data from a memory cell array that is selected by the column address and a row address. The output distribution signal generation circuit generates an output distribution signal from the activation data based on the data selection signal and the internal control signal.